Welcome to this course - Advanced topics in SystemVerilog Verification Methodology (VMM/Pre-UVM). As with many of our other courses on Udemy we use a hybrid approach of slides + presenter + whiteboard to make the learning more dynamic than slide-plus-audio-only style. Feel free to contact us if you want a more seasoned, slide-plus-audio type course with labs etc. We will be glad to assist you with the same.

Objectives

• To appreciate key concepts behind factory OOP pattern

• Appreciate callback and other design patterns as it applies to verification

• Learn how sequences/scenarios help in verification

• Understand how a Scheduler - like that of UVM Sequencer - works

Prerequisites

Audience must be familiar with Verification features of SystemVerilog and basic methodology (VMM/UVM). If you need to get started, we suggest you look at our Udemy course titled: SystemVerilog Verification Methodology - using VMM (Pre-UVM)

Topics covered

• Factory pattern

  • Introduction, requirements

  • Methods

  • Using factory to change the generator output

• Callbacks

  • Introduction, requirements

  • Façade class declaration

  • Adding the callback hook in transactor

  • Populating the callback method

  • Registering callbacks

  • Error Injection example

• Scenario Generator - precursor to UVM Sequences

  • Array randomization woes in SV

  • Using pre-built scenario generator

  • In-depth view of scenario generator

  • Extending scenario generator

  • Tweaking election policy

• Notifications in VMM - UVM events complimentary

  • Define, configure, notify, sync

  • Get status/transaction

  • Different types of notifications

  • Sample applications

• Scheduler (similar to UVM Sequencer)

• Broadcaster

Slides use VMM base class library, however concepts are applicable to UVM as well. Also the narration relates relevant UVM counterparts thereby making the connection easier for users to appreciate